Many time to digital converters (TDCs) nowadays use single-ended ring oscillators or differential topologies with small latches for synchronization of the two independent running single-ended ring oscillators or delay lines. The advantage of differential ring oscillators or delay lines over single-ended topologies is 20 dB more power supply rejection ratio (PSRR). In addition, differential ring oscillators and delay lines do not suffer from even and odd delay dependency due to process induced mismatch between rising and falling edge.
Today's single-ended ring oscillators and delay line topologies are used with tolerating the disadvantages of reduced power supply rejection ratio performance, which lead to increased supply ripple and noise requirement. The single-ended topology has even/odd delay variations as explained above, therefore the time to digital converter quantization noise floor increases. The increased quantization noise floor leads to, for example in wireless transmitters, EVM degradation (EVM error vector magnitude). In the currently used modulation schemes the EVM performance is sufficient but future modulation schemes and ADPLL topologies (ADPLL—all digital phase locked loop) will ask for a better TDC noise performance. Conventional differential ring oscillators or delay lines use small latches as a synchronization technique. These additional latches increase the intrinsic delay and therefore the quantization noise floor of the TDC even when resolution enhancement techniques as multipath or resistive interpolation are used.